Compute performance demand has been growing exponentially in recent years, and with the advent of Generative AI, this demand is growing even faster. Moore’s law coming to an end as well as the Memory Wall (bandwidth & capacity) are the main performance bottlenecks. The chiplet system-in-package (SiP) is the industry's solution to these bottlenecks. Silicon interposers are the industry’s main technology to connect chiplets in SiPs, but they introduce several new bottlenecks. The largest interposer going to production is 2700mm2, which is ~1/4 the largest standard package substrate. Thus, a SiP with a silicon interposer has limited compute & memory chiplets, thus limited performance.
This presentation introduces Universal Memory Interface (UMI), a high bandwidth efficient D2D connectivity technology between compute and memory chiplets. UMI PHY on standard packaging provides similar bandwidth/power to D2D PHYs with silicon interposers, thus enabling the creation of large & powerful SiPs required to address Gen AI applications.
Ramin Farjadrad
Ramin Farjadrad is the inventor of over 130 granted and pending patents in communications and networking. He has a successful track record of creating differentiating connectivity technologies adopted by the industry as International standards (Two Ethernet standards at IEEE, one chiplet connectivity at OCP.) Ramin co-founded Velio Communications, which led to a Rambus/LSI Logic acquisition, and Aquantia, which IPO’d and was acquired by Marvell Technologies. Ramin’s Ph.D. EE is from Stanford.
